1. Field of the Invention
The invention generally relates to a semiconductor component and a manufacturing method thereof, and more particularly, to a semiconductor package structure and a manufacturing method thereof.
2. Description of Related Art
The chip package is for protecting a bare die, reducing density of chip bonding spots and providing a chip with good heat-dissipating. When the count of chip contacts is ceaselessly increased and the chip area is made smaller and smaller with the development of semiconductor technology, it is difficult to re-distribute all contacts of a chip in area array scheme on the surface of the chip. Even though a chip surface can accommodate all the contacts thereof, the interval between contacts still gets too small so as to affect the electrical reliability as the successive soldering process of solder balls.
In this regard, the prior art provides a scheme that, first, a molding compound is used to package a chip for increasing the chip area, in which an active surface of the chip and a bottom surface of the molding compound are exposed out; then, a redistribution circuit layer is formed on the active surface of the chip and the bottom surface of the molding compound and multiple solder balls are formed respectively on the contacts of the redistribution circuit layer to serve as an electrically connecting medium between the chip and the external contacts. That is to say, the active surface of the chip and the solder balls are located on a same plane. However, it is easier to produce overflow during packaging, which leads the molding compound to extend onto a part of the active surface and increases the production fraction defective. Further, the molding compound would contaminate the active surface of the chip so that the above-mentioned packaging scheme is unable to be used in CMOS chip.
Moreover, in the prior art, the chip area is increased by means of packaging a chip with molding compound, the redistribution circuit layer is located only on the active surface of the chip and the surface of the molding compound, in which the surface of the molding compound and the active surface of the chip have a same direction so that multiple chips are unable to be stacked. As a result, the conventional scheme is unable to use vertical stacking method to package multiple semiconductor components (for example, multiple chips) in a same package structure. In this regard, how to effectively reduce the thickness and size of a package structure of multiple stacked chips and meanwhile look after the electrical reliability of the package structure has become a project to be solved in strong desire.